There is currently a trend among manufacturers of integrated circuits to increase the number (e.g., the density) of circuits on a single chip to achieve higher levels of performance and greater functionality. As integrated circuits have become more dense, the ability to test such integrated circuits by conventional techniques has become increasingly more difficult. To overcome this difficulty, much effort has been devoted to accomplishing built-in self-testing of such integrated circuits by configuring them with circuitry for that purpose.
To date, there have been several known types of built-in self-test (BIST) circuits, including BILBO (Built-In Logic Block Observer) and "circular" BIST. These approaches are not without their disadvantages. One critical disadvantage is that current BIST circuits often require a trade-off between fault coverage (as defined by the percentage of total possible faults that can be diagnosed) and overhead penalty (as defined by the percentage of the total area of the integrated circuit that must be devoted to the BIST circuit). Obviously, the greater the amount of the area of the integrated circuit that must be dedicated to a BIST circuit, the less the amount of area available for implementing the normal or regular function of the chip. For this reason, BIST circuits which impose a high overhead penalty, say above 20% of the total chip area, are not favored even through such BIST circuits may achieve high fault coverage.
Yet another disadvantage of current BIST circuits is that few if any offer the ability to test more than the integrated circuit in which such circuitry is incorporated. The lack of flexibility of current BIST circuitry to accomplish testing at the circuit board, or even at the system level, often imposes inefficiencies during testing.
Thus, there is a need for a BIST circuit, for incorporation with a device, which overcomes the above-enumerated disadvantages.